1. Field of the Invention
The present invention relates to a data/clock recovery circuit for recovering a high-rate clock signal and data with high accuracy in high-speed serial communication.
2. Description of Related Art
For example, the USB (Universal Serial Bus) 2.0 standard is a very high-speed serial communication standard with a communication rate of 480 MBPS (megabits per second).
Generally, a communication line consists of a total of four lines, a power supply line, a ground line and a pair of data lines (D+, D−). Thus, a clock signal is not fed through the communication line.
Thus, it is necessary for the serial transmission without the clock signal supplied to recover the clock signal from the received data fed from the data line, and to sample the received data using the clock signal recovered. A circuit for recovering the clock signal and data from the received data is called a data/clock recovery circuit.
As a conventional example of the data/clock recovery circuit, the following document is known.
Dao-Long Chen, “A Power and Area Efficient CMOS Clock/Data Recovery Circuit for High-Speed Serial Interfaces”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.31, NO.8 AUGUST 1996.
With the foregoing configuration, the conventional data/clock recovery circuit has the following problem. Since the jitter components on the data line are very large such as 0.4 UI (Unit Interval) and the transmission rate is very high such as 480 MBPS in the USB 2.0 standard, it is difficult to apply the conventional data/clock recovery circuit.